IMEC, which works with core commercial partners in semiconductor research and is presenting a number of papers at the International Electron Devices Meeting (IEDM) in San Francisco, California, this week.
For the paper on 5nm embedded MRAM IMEC performed a design analysis using a silicon-verified compact model of a pMTJ made to be compatible with the 5nm node. The pMTJ has nominal access latency of less than 2.5ns and less than 7.1ns for read and write operations, respectively. The analysis shows that STT-MRAM meets numerous requirements for level-one through level-three caches in high-performance computing and offers significant energy gains over SRAM for both read and write accesses. It meets target clock frequencies of more than 100MHz while occupying 43.3 percent of the area of the SRAM macro.
IMEC performed a design-technology co-optimization (DTCO) to define the requirements and specifications for STT-MRAM cells at the 5nm node and concluded that a high-performance STT-MRAM bit cell with the MRAM pitch being twice the contacted gate pitch of 45nm is the preferred solution for last-level caches at 5nm. In a second step, a high-performance STT-MRAM cell was fabricated on 300mm Si wafers and the characteristics of the magnetic tunnel junction were measured experimentally.
Energy comparison between SRAM and STT-MRAM by cache size. STT-MRAM becomes more energy efficient compared to SRAM at 0.4MB for read, and 5MB for write operations. Source: IMEC.
An examination of the energy profile for both SRAM and STT-MRAM showed the researchers that there are two cross-over points that impact system energy consumption: when STT-MRAM read and write energy becomes lower than that of SRAM at 0.4Mbytes an 5Mbytes. This is due to the exponential increase of SRAM standby power with increasing memory capacity.
The researchers conclude that at the 5nm node and cache capacities of less than 12Mbytes STT-MRAM is beneficial regardless of read-write asymmetry and irrespective application profile.
"For the first time, DTCO and silicon-verified models allowed us to conclude that the STT-MRAM energy becomes more efficient as compared to SRAM for high-density memory cells beyond 0.4Mbytes and 5Mbytes density for read and write operations, respectively. The comparison also reveals that the latency of the STT-MRAM is sufficient to meet the requirements of the last-level caches in the high-performance computing domain, which operate around 100MHz clock frequency," said Gouri Sankar Kar, program director at IMEC, in a statement.
It should be considered that further improvements are expected to come with spin-orbit torque MRAMs now emerging from research and that show superior characteristics.
Headquartered in Chandler, Arizona,
Everspin Technologies, Inc. is the worldwide leader in designing, manufacturing, and commercially shipping discrete and embedded Magnetoresistive RAM (MRAM) and Spin-Torque MRAM (ST-MRAM) into markets and applications where data persistence and integrity, low latency, and security are paramount. With over 70 Million MRAM and ST-MRAM products deployed in data center, cloud storage, energy, industrial, automotive, and transportation markets, Everspin has built the strongest and fastest growing foundation of MRAM users in the world.
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